<?xml version="1.0" encoding="utf-8" standalone="yes"?><rss version="2.0" xmlns:atom="http://www.w3.org/2005/Atom"><channel><title>TAI</title><link>https://mimera.github.io/</link><description>Recent content on TAI</description><generator>Hugo</generator><language>en</language><managingEditor>imera@espol.edu.ec (Some Person)</managingEditor><webMaster>imera@espol.edu.ec (Some Person)</webMaster><lastBuildDate>Sun, 17 Nov 2024 20:07:56 -0500</lastBuildDate><atom:link href="https://mimera.github.io/index.xml" rel="self" type="application/rss+xml"/><item><title>People</title><link>https://mimera.github.io/people/</link><pubDate>Sun, 17 Nov 2024 20:07:56 -0500</pubDate><author>imera@espol.edu.ec (Some Person)</author><guid>https://mimera.github.io/people/</guid><description>&lt;p>Maria Isabel Mera Collantes - PI&lt;/p>
&lt;ul>
&lt;li>Professor at the Faculty of Electrical Engineering and Computer Science of the Escuela Superior Politécnica del Litoral (FIEC-ESPOL).&lt;/li>
&lt;li>Ph.D. in Electrical Engineering from New York University in 2021.&lt;/li>
&lt;li>M.Sc. in Electrical Engineering from Stony Brook University as a Fulbright Scholar.&lt;/li>
&lt;li>Stint in industry: Google - TPU chip design team and Intel - GPU design team.&lt;/li>
&lt;li>Her research interests lie in the intersection of trustworthy computer architecture design, hardware verification, reconfigurable systems, embedded systems and data networks.&lt;/li>
&lt;/ul>
&lt;p>Current researchers:&lt;/p></description></item><item><title>Research</title><link>https://mimera.github.io/research/</link><pubDate>Sun, 17 Nov 2024 20:07:46 -0500</pubDate><author>imera@espol.edu.ec (Some Person)</author><guid>https://mimera.github.io/research/</guid><description>&lt;p>My research interests lie at the intersection between
hardware architecture for neural networks, hardware security,
low power and Edge AI.&lt;/p>
&lt;h2 id="publications">Publications&lt;/h2>
&lt;ol start="5">
&lt;li>M. I. Mera Collantes, Z. Ghodsi and S. Garg, &amp;ldquo;SafeTPU: A Verifiably Secure Hardware Accelerator for Deep Neural Networks,&amp;rdquo; 2020 IEEE 38th VLSI Test Symposium (VTS), San Diego, CA, USA, 2020, pp. 1-6, doi: 10.1109/VTS48691.2020.9107564.&lt;/li>
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&lt;li>M. I. Mera Collantes and S. Garg, &amp;ldquo;Do Not Trust, Verify: A Verifiable Hardware Accelerator for Matrix Multiplication,&amp;rdquo; in IEEE Embedded Systems Letters, vol. 12, no. 3, pp. 70-73, Sept. 2020, doi: 10.1109/LES.2019.2953485.&lt;/li>
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&lt;li>Maria Isabel Mera, Jonah Caplan, Seyyed Hasan Mozafari, Brett H. Meyer, and Peter Milder. 2017. Area, Throughput, and Power Trade-Offs for FPGA- and ASIC-Based Execution Stream Compression. ACM Trans. Embed. Comput. Syst. 16, 4, Article 96 (November 2017), 20 pages. &lt;a href="https://doi.org/10.1145/3063312">https://doi.org/10.1145/3063312&lt;/a>&lt;/li>
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&lt;li>M. I. Mera Collantes, M. El Massad and S. Garg, &amp;ldquo;Threshold-Dependent Camouflaged Cells to Secure Circuits Against Reverse Engineering Attacks,&amp;rdquo; 2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Pittsburgh, PA, USA, 2016, pp. 443-448, doi: 10.1109/ISVLSI.2016.89.&lt;/li>
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&lt;li>J. Caplan, M. I. Mera, P. Milder and B. H. Meyer, &amp;ldquo;Trade-offs in execution signature compression for reliable processor systems,&amp;rdquo; 2014 Design, Automation &amp;amp; Test in Europe Conference &amp;amp; Exhibition (DATE), Dresden, Germany, 2014, pp. 1-6, doi: 10.7873/DATE.2014.106.&lt;/li>
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&lt;li>M. I. Mera and R. L. Estrada, &amp;ldquo;Model Based Design of an Adaptive Transmission Module for Non-Line of Sight OFDM System (WiMAX),&amp;rdquo; 2009 Spanish Conference on Electron Devices, Santiago de Compostela, Spain, 2009, pp. 204-206, doi: 10.1109/SCED.2009.4800466.&lt;/li>
&lt;/ol>
&lt;h2 id="teaching">Teaching&lt;/h2>
&lt;ul>
&lt;li>2024-II Embedded Systems&lt;/li>
&lt;li>2024-I Data Networks&lt;/li>
&lt;/ul></description></item></channel></rss>