Research

My research interests lie at the intersection between hardware architecture for neural networks, hardware security, low power and Edge AI.

Publications

  1. M. I. Mera Collantes, Z. Ghodsi and S. Garg, “SafeTPU: A Verifiably Secure Hardware Accelerator for Deep Neural Networks,” 2020 IEEE 38th VLSI Test Symposium (VTS), San Diego, CA, USA, 2020, pp. 1-6, doi: 10.1109/VTS48691.2020.9107564.
  1. M. I. Mera Collantes and S. Garg, “Do Not Trust, Verify: A Verifiable Hardware Accelerator for Matrix Multiplication,” in IEEE Embedded Systems Letters, vol. 12, no. 3, pp. 70-73, Sept. 2020, doi: 10.1109/LES.2019.2953485.
  1. Maria Isabel Mera, Jonah Caplan, Seyyed Hasan Mozafari, Brett H. Meyer, and Peter Milder. 2017. Area, Throughput, and Power Trade-Offs for FPGA- and ASIC-Based Execution Stream Compression. ACM Trans. Embed. Comput. Syst. 16, 4, Article 96 (November 2017), 20 pages. https://doi.org/10.1145/3063312
  1. M. I. Mera Collantes, M. El Massad and S. Garg, “Threshold-Dependent Camouflaged Cells to Secure Circuits Against Reverse Engineering Attacks,” 2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Pittsburgh, PA, USA, 2016, pp. 443-448, doi: 10.1109/ISVLSI.2016.89.
  1. J. Caplan, M. I. Mera, P. Milder and B. H. Meyer, “Trade-offs in execution signature compression for reliable processor systems,” 2014 Design, Automation & Test in Europe Conference & Exhibition (DATE), Dresden, Germany, 2014, pp. 1-6, doi: 10.7873/DATE.2014.106.
  1. M. I. Mera and R. L. Estrada, “Model Based Design of an Adaptive Transmission Module for Non-Line of Sight OFDM System (WiMAX),” 2009 Spanish Conference on Electron Devices, Santiago de Compostela, Spain, 2009, pp. 204-206, doi: 10.1109/SCED.2009.4800466.

Teaching

  • 2024-II Embedded Systems
  • 2024-I Data Networks